View EDOSK2674_7707048.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
EDOSK2674 u ser m anual f or h8/2674r m icrocomput er
preface cautions 1. this document may be, wholly o r partially, subje c t to change wit hout notice. 2. all rights reserved. no one is permitted to rep r oduc e or duplicate, in any for m, a part or this entire document without hitachi micro systems europe limited's written permission. trademarks general all brand or product names u s ed in this man ual are tradem a r ks or registere d trademarks of their respective companies or organisations. specific microsoft, ms and ms-dos are register ed tradema r ks and windows and windows nt a r e trademarks of microsoft corporati on. document information product code: d003680_11 version: 01.1 date: 21/11/2002 copyright ? hitachi micro syste m s europe ltd. 1995-2002. all rights reserved. 2
t a ble of content s t able of c onte nts ............................................................................................................................... ........................ 3 1. i ntroduction ............................................................................................................................... ........................ 5 1.1. EDOSK2674 ge neral board layout................................................................................................. ......... 5 1.2. EDOSK2674 actual board l ayout.................................................................................................. ........... 6 2. EDOSK2674 b l o ck d iagram .............................................................................................................................. 7 2.1. power suppl y ................................................................................................................... .............................. 7 2.2. operating m o des ................................................................................................................ .......................... 7 2.3. h8/2674r microcomputer ......................................................................................................... ................... 8 2.4. boot flash m e mory .............................................................................................................. ........................ 8 2.5. main flash m e mory .............................................................................................................. ......................... 9 2.6. ram ............................................................................................................................ ......................................... 9 2.7. sdram .......................................................................................................................... ....................................... 9 2.8. lan control l er ................................................................................................................. ............................ 9 2.9. real time cl ock ................................................................................................................ ........................... 10 2.10. switches ....................................................................................................................... .................................. 10 2.11. indicators ..................................................................................................................... ................................ 10 3. e xternal i nter faces ............................................................................................................................... ......... 11 3.1. serial interface ............................................................................................................... .......................... 11 3.2. lan interface .................................................................................................................. ............................. 12 3.3. expansion conne ctor ............................................................................................................ .................. 13 3.4. auxiliary i/o header ........................................................................................................... ........................ 14 4. b oard o ptions ............................................................................................................................... ................... 16 4.1. jumper links ................................................................................................................... .............................. 16 4.2. rtc back u p supply .............................................................................................................. ....................... 16 4.3. remote switch .................................................................................................................. ........................... 17 4.4. crystal choi ce ................................................................................................................. ........................... 17 4.5. removable component i n formati o n. ............................................................................................... ... 18 4.6. additi onal component i n formati o n. .............................................................................................. .... 18 5. s tart - up i nstr uctions ............................................................................................................................... ....... 19 6. c ode d evelopm e nt ............................................................................................................................... ............ 20 6.1. flash programming .............................................................................................................. ..................... 20 6.2. test menu ...................................................................................................................... ................................. 20 6.3. hdi-m on i t or .................................................................................................................... ............................... 20 7. s oftware ............................................................................................................................... ............................ 21 7.1. EDOSK2674 m e mory map ........................................................................................................... .................. 21 7.2. h8/2674r re gi ster confi g urati on ................................................................................................ ......... 23 8. m echanical d ra w i n g ............................................................................................................................... ......... 33 9. d esigning an e x p ansion c ard .......................................................................................................................... 34 9.1. mechanical ..................................................................................................................... ............................... 34 3
9.2. functi onal ..................................................................................................................... ................................ 34 10. a dditional i nformation ............................................................................................................................... ..... 38 4
1. i ntro du ction the EDOSK2674 is an evaluation development ope r ating system kit designed around the hitachi h8/2674r microcomputer (mcu). the edosk267 4 operates from a single 5v supp ly. only two modes of operation: boot mode and normal mode. 33mhz bus clock speed. the edosk267 4 card provides the following inte rfaces: ? one serial communication interf ace up to 115200kbs with no errors. ? a standard rj45 ethernet interf ace provides co nnection to a lo cal area network (includes l i nk and activity indic a tors ). ? a 140-way high-density conne ct or for interface t o a bus expansion card. ? position for a 50 way auxiliary i/o header to allow connection to all unused mcu i/o pins and power. the edosk267 4 card is provide d with the following memory types and densitie s: ? 512kbytes (8-bit x 512) boot flash memory ? 4mbytes (16-bit x 2m) main flash memory ? 8mbytes (16-bit x 4bank x 1m) sdram memo ry a real-time clock (rtc) is fitted to the edosk26 74 to provide current date and time information to the mcu. 1.1. EDOSK2674 g en er a l b oard l ay out the general boa rd layout shows the posit ion of all major parts of the board. re s e t jum p ers 160.00m m 10 0. 00mm nm i 5v i n pu t la n rj 4 5 h 8 s / 267 4r xt a l l a n co nt ro ll e r s dra m 8m b ma i n fl ash 4m b rt c xta l bo o t fl ash 5 12k b ba tt e r y xt a l 74 - 02 xt a l 3v 74 - 12 5 74 - 14 3v 1 40-w a y, e x p ans i o n c onn ec t o r a1 se r i a l po r t 9-w a y fem a l e au x ili a r y i/o ( n ot fitt ed) po we r ti m e r boot rt c_ ba t t e ry nm i rese t j10 j9 j8 b1 ee p 232 fig u re 1-1: e d osk general b o ard lay o u t 5
1.2. EDOSK2674 a ctual b oard l ay out the actual board layout shows t he real position of a ll component s, the reference numbers and silk screen labellin g. figure 1-2: e d osk ac tual board layout 6
2. edosk 2674 b lock d iagram the edosk267 4 is designed around a h8/2674r mcu and incl udes flash memory, sdram, real-time clock, a n interface to a local expansion card, an interface for io connections, a serial port and a lan port. the figure below shows the block diagram of the EDOSK2674 bo ard. h8s 26 74r l q fp 144 sdram 8m b y t e boot f l ash 5 12k byt e main f l ash 4m b y t e lan 10 m bps rt c rs 2 3 2 xt a l & bat t e x pa ns i o n c o nn ec t o r m e m o ry m app ed peri ph erals rj45 db9 (fem a l e) au x iliary i/ o con n e c t o r i / o p e ri p herals pow e r jack 3. 3v r e g x2 f igure 2-1: edosk b lock d iagram 2.1. p ower s upp l y the edosk hardware requi res a pow er supply of +5v. sin c e total power co ns umption can vary widely due to external connections, port states, and me mory configuration, use a pow er supply capable of providing at least 500ma at +5v dc 5% . the design is sp ecified for evalu a tion of the mcu and so does not include circu i t r y for supply filte r ing/noise reduction, under voltage protectio n , over current p r otection or reve rsed polar ity pro t ection. caution should be used when selecting and using a power supply. the power conn ector on the edosk is a 2.5mm barrel c onnector. the center pin is the posit ive connection. f igure 2-2: p ower s upply c onnec t ion cauti o n: existi ng c u stomers using e6000 pr oduc ts note tha t the polarity of this board is opposi t e to that for the e6000. use of the e6000 powe r supply wi th this boa rd will da mage both boa rd and power s u pply. 2.2. o p e rating mode s the h8/2674r h a s only two mod e s of operation set by jumper configuration: mode 1: (md2=0 , md1=0, md0=1) advanced, external data bus initial width is 16 bits. ? edosk normal mode. mode 2: (md2=0 , md1=1, md0=0) advanced, external data bus initial width is 8 bits. ? edosk boot mode. the h8/2674r has no internal flash memory. on power-up th e edosk mode (boot or no rma l ) selects the flash memory from which the h8/2674r first accesse s. 7
2.3. h8/2674r m icrocomp uter the mcu is an h8/2674r deri v ative of the h8/2600 series microprocessor with an internal 16-bit architecture, sixteen 16-bit ge neral registers and 69 basic in structions. the mcu contai ns a number of on-chip facilities, including: ? 33mhz maximum operating freq uency ? voltage: 3.3v ? 24 bit external a ddress bus, 16 b i t external data b u s ? 33mhz max external bus frequency ? 7 areas of external address spa c e, each 2mbyte s ? supports direct sdram interface ? various peripheral functions: dma c ontroller ( d mac) exdma controller (exdmac) data trans fer c o ntroller (d tc ) 16-bit timer-pulse unit (tpu) programmable p u lse generator (ppg) 8-bit timer (tmr) watchdog timer (wdt) asynchronous serial communica tion interface (sci) 10-bit a/d converter 8-bit d/a converter clock pulse gen erator ? on-c hip memory : 32kbytes ram ? general i/o po rt s: i/o pins: 103 input-only pins: 12 2.4. boot f lash m emor y the boot flash memory is a 512k x 8bit plcc device (a md 29lv040b) and is f i tted to a socket on the edosk2 674. the mcu inte rfa c es with the boot flash on reset in area 0 only when the edos k is set to boot mode. the same boot flash is also a ccessible in area 7 w hen the edosk is set to eit her boot or no rmal mode. in normal mode the boot flash is designed to r e side in area 7 o n ly. the boot flash may be removed from it s so cket to be programmed by a dedicat ed programm e r or alternately it may b e programmed in system when th e boot write enable jumper is fitt ed. details of bsc register settings f o r the amd flas h boot memory can be found in section 7.2. boot flash acce ss: bus width: 8 bit. access states: 3 wait states: 3 cycle burst: 6 (area 0 only) 8
extended cs period: t h and t t (a rea 7 only) 2.5. main f lash m emor y the main flash memory is a 4mbyte devic e (intel 28f320j3a) and is word accessed. the mcu inte rfa c es with the mai n flash on reset in area 0 only when the edosk is set to normal mode. in normal mode the main flash is designed to re side in area 0 an d area 1. in boot mode the main flash is designed to resi de in area 1 only and is paged by driving port pin 33. the main flash may be programmed in system w hen write enable jumper is fitted. details of bsc register settings f o r the intel flash memory can be found in section 7.2. main flash acce ss: bus width: 16 bit. access states: 3 wait states: 2 cycle burst: 6 2.6. ram the h8/2674r h a s 32kb of ram available on-chip. this ram can be enabled or disabled by means of the rame bit in the system control r egister (syscr). initiall y thi s ram is enabled. 2.7. sdram the h8/2674r, external address space areas 2 to 5, has been designated as continuous syn c hronous dram space. an 8mb external sdram interface s directly to the mcu. the sdram us ed is a micron mt48lc4m16a 2: row addressing: 4k (a0-a11) bank addressing : 4 (ba0, ba1) column addressing: 512 (a0-a8) mcu port pin 34 is used to drive the sdram cs pin. details of bsc a nd dram regist er settings for the sdram can be found in sectio n 7.2. sdram access: bus width: 16 bit. 2.8. lan c ontro ller the lan controller ic is a smsc lan91c96 device. the base a ddress of th is de vice defaults to 300h, however the edosk re-maps this to f80000h. the mac address is containe d within a removable eeprom connected to t he controller. this is programmed during production testin g and should not be altered. details of bsc register settings f o r the lan controller can be foun d in section 7.2. lan contr o ller access: bus width: 8 bit. access states: 3 wait states: 3 extended cs period: t h and t t 9
2.9. r ea l t im e c lock the edosk is supplied with a real time clock (rtc) and batte ry backup (when fitted) for current date and time in formation. a cell retainer (j11) is used to ho ld a cell battery t o keep time data correct when system supply is r e moved. the rtc is a dallas/maxim ds1672u device tha t interfaces to th e h8/2674r via an i2c bus. - scl ? serial clock (mcu port pi n 31) - sda ? serial data (mcu po rt pin 32) a coin-cell batt e ry between 1. 3v and 3.6v of 12mm diamete r and 3.175mm maximum height may be inserted into the edosk to allow timekeeping eve n when power to the board is removed. battery referen c e: br1216, cr1216, br1220, cl1220, cr122 0 and br1225 2.10. s witches the edosk pro v ides two button s for influencing the operation of the board. the purpose of each button is clearly marked next to it. refer to the board layout for positions (section 1). ? reset swi t ch this button provides the mcu wit h a timed reset pulse of at least 2 50ms. ? nmi swi t ch the nmi button on this edosk provides the mcu with a positive pulse to generate a non-maskable interrupt. 2.11. i ndic a tors three red leds are fitted to the pcb. the function of each r ed l e d is clearly ma rked on the silk screen of the pcb. please refer to the board layout diagram fo r position information (section 1). power: when the board is con nected to a power source this le d will il luminate. boot: when th e edosk has been placed into boot mode this led will il lumina te. timer: dedicat ed for user control and is dr iven by the mcu wat c hdog timer ov erflow pin. 10
3. e xternal i nterf a ces connector locations and pin orie ntation for expansion and aux iliary io (right-ang led 50- way idc) is shown below: pi n 1 a u x i l i a r y i o e x p a n s i o n c o n n e c t o r serial ethernet po w e r e d o s k 2 6 7 4 pin a 1 not e : a u x i liary io connect or is not fitt ed as s t andard 3.1. s er ia l i nte r face the serial com m unication interface (sci-3) on t he mcu directly supports three-wire serial interfaces. the edosk p r o v ides the mcu with an external clock source at 1.8432mhz. this provides a fixe d baud rate of 11520kbps for the serial port with zero erro rs (irre spective of the operating crystal frequency). a hyper terminal link between th e edosk and a pc will enable th e user interface. ? link to a hyper terminal ? connect at baud rate 115200, 8 bits, no parity, 1 stop bit the edosk rs232 interface conforms to data communication equipment (dce) format allowing the use of 1-1 cable s when connected to data terminal equipment (dte) such as an ibm pc. handshaking is not su pported as stan dard on the mcu so for normal use a minimal three-wire cable can be us ed. the minimum connections are not shaded in the following table. edo s k db9 con n ect or pin s i g n a l h o s t d b 9 con n ect or pin 1 no connection 1 2 edo sk tx host rx 2 3 edo sk rx host tx 3 4 no connection 4 5 g r o u n d 5 6 no connection 6 7 no connection 7 8 no connection 8 9 no connection 9 t able 3-1: rs232 i n t erface c onn e ctio ns 11
1 2 3 4 5 6 7 8 9 figure 3-1: e d osk serial port pin numberi n g 3.2. lan i nte r face a 10mhz lan connection is pro v ided through a standard rj45 interface. two leds are in tegrated into the ethernet connector and give the following indicat i on: green: link indicator. reflects t he integrity statu s . yellow: activity i ndicator. activat ed by transmit or receive activit y . pi n n a m e di r ecti o n descr i p ti o n rj1 txd+ out put from t he ed osk transmit dat a posit i ve rj 2 txd- out put from t he ed osk transmit dat a negative rj 3 rxd+ i nput f r om t he lan receive dat a posit i ve rj 4 n/ c not connect ed rj 5 n/ c not connect ed rj 6 rxd- i nput f r om t he lan receive dat a negat ive rj 7 n/ c not connect ed rj 8 n/ c not connect ed t able 3-2: lan i nte r face c onnection s rj1 r j8 figure 3-2: e d osk lan por t pin numberi n g 12
3.3. e xp ans ion c onne ctor the edosk exp ansion bus conn ector is a 140-way jae kx14-14 0k5d and has the following pin connections: col : a assi gnment type i / o h8s2674r col : b assi gnment type i / o h8s2674r 1 g n d - - g n d 1 g n d - - g n d 2 cki o o o u t sys. cl k 2 g n d - - g n d 3 g n d - - g n d 3 g n d - - g n d 4 d 0 t i / o d 0 4 d 1 t i / o d 1 5 d 2 t i / o d 2 5 d 3 t i / o d 3 6 d 4 t i / o d 4 6 d 5 t i / o d 5 7 d 6 t i / o d 6 7 d 7 t i / o d 7 8 g n d - - g n d 8 g n d - - g n d 9 d 8 t i / o d 8 9 d 9 t i / o d 9 10 d 1 0 t i / o d 1 0 10 d 1 1 t i / o d 1 1 11 d 1 2 t i / o d 1 2 11 d 1 3 t i / o d 1 3 12 d 1 4 t i / o d 1 4 12 d 1 5 t i / o d 1 5 13 g n d - - g n d 13 g n d - - g n d 14 d 1 6 t i / o n o connect 14 d 1 7 t i / o n o connect 15 d 1 8 t i / o n o connect 15 d 1 9 t i / o n o connect 16 d 2 0 t i / o n o connect 16 d 2 1 t i / o n o connect 17 d 2 2 t i / o n o connect 17 d 2 3 t i / o n o connect 18 g n d - - g n d 18 g n d - - g n d 19 d 2 4 t i / o n o connect 19 d 2 5 t i / o n o connect 20 d 2 6 t i / o n o connect 20 d 2 7 t i / o n o connect 21 d 2 8 t i / o n o connect 21 d 2 9 t i / o n o connect 22 d 3 0 t i / o n o connect 22 d 3 1 t i / o n o connect 23 3. 3 v - - 3. 3 v 23 3. 3 v - - 3. 3 v 24 3. 3 v - - 3. 3 v 24 3. 3 v - - 3. 3 v 25 n c 0 o p t i o n opt i o n n o connect 25 3. 3 v - - 3. 3 v 26 a 0 o o u t a 0 26 a 1 o o u t a 1 27 a 2 o o u t a 2 27 a 3 o o u t a 3 28 a 4 o o u t a 4 28 a 5 o o u t a 5 29 a 6 o o u t a 6 29 a 7 o o u t a 7 30 g n d - - g n d 30 g n d - - g n d 31 a 8 o o u t a 8 31 a 9 o o u t a 9 32 a 1 0 o o u t a 1 0 32 a 1 1 o o u t a 1 1 33 a 1 2 o o u t a 1 2 33 a 1 3 o o u t a 1 3 34 a 1 4 o o u t a 1 4 34 a 1 5 o o u t a 1 5 35 g n d - - g n d 35 g n d - - g n d 36 a 1 6 o o u t a 1 6 36 a 1 7 o o u t a 1 7 37 a 1 8 o o u t a 1 8 37 a 1 9 o o u t a 1 9 38 a 2 0 o o u t a 2 0 38 a 2 1 o o u t a 2 1 39 a 2 2 o o u t a 2 2 39 a 2 3 o o u t a 2 3 40 a 2 4 - - n o connect 40 a 2 5 o o u t n o connect 41 g n d - - g n d 41 g n d - - g n d 42 / d a c k 0 o o u t / d a c k 0 42 / d a c k 1 o o u t / d a c k 1 43 / d r e q 0 i , p - u p i n / d r e q 0 43 / d r e q 1 i , p - u p i n / d r e q 1 44 g n d - - g n d 44 g n d - - g n d 45 / c s 0 o , p - u p o u t / c s 0 45 / c s 1 o , p - u p o u t / c s 1 46 / c s 2 o o u t n o connect 46 / c s 3 o o u t n o connect 47 / c s 4 o o u t n o connect 47 / c s 5 o o u t n o connect 48 / c s 6 o , p - u p o u t / c s 6 48 r/ w o o u t n o connect 49 g n d - - g n d 49 g n d - - g n d 50 / r d o o u t / r d 50 / b s o o u t / a s 13
col : a assi gnment type i / o h8s2674r col : b assi gnment type i / o h8s2674r 51 g n d - - g n d 51 g n d - - g n d 52 / w e 0 o o u t / l w r 52 / w e 1 o o u t / h w r 53 / w e 2 o o u t n o connect 53 / w e 3 o o u t n o connect 54 g n d - - g n d 54 g n d - - g n d 55 / w a i t 0 i , p - u p i n / e x p _ w a i t 55 / w ai t1 i , p - up i n no connect 56 / w ai t2 i , p - up i n no connect 56 / w ai t3 i , p - up i n no connect 57 g n d - - g n d 57 g n d - - g n d 58 /irq1 i , p - u p i n /irq1 58 /irq2 i , p - u p i n /irq2 59 /irq3 i , p - u p i n /irq3 59 /irq4 i , p - u p i n /irq4 60 /irq5 i , p - u p i n /irq5 60 / i r q6 i , p - up i n no connect 61 / i r q7 i , p - up i n no connect 61 / i r q8 i , p - up i n no connect 62 + 5 v - - + 5 v 62 + 5 v - - + 5 v 63 + 5 v - - + 5 v 63 + 5 v - - + 5 v 64 n c 1 o p t i o n opt i o n n o connect 64 + 5 v - - + 5 v 65 / r e s o o u t / r e s e t 65 + 5 v - - + 5 v 66 a + 5 v - - + 5 v 66 + 5 v - - + 5 v 67 a + 5 v - - + 5 v 67 n c 2 o p t i o n opt i o n n o connect 68 n c 3 o p t i o n opt i o n n o connect 68 n c 4 o p t i o n opt i o n n o connect 69 n c 5 o p t i o n opt i o n n o connect 69 n c 6 o p t i o n opt i o n n o connect 70 n c 7 o p t i o n opt i o n n o connect 70 n c 8 o p t i o n opt i o n n o connect t able 3-3: e xp ansi o n b us c onnection s o = not buffe red output. i = not buffered input. p-up = pull up resistor. expansion card s to be fitted to the edosk should use jae connector kx15-140k2d and should only ha ve discrete components fitte d to the under side with a maximum height of 2mm. 3.4. a ux iliary i/o h e ade r position for a 50 way auxiliary i/o header is provided on the edosk to allow connection to all unused mcu i/o pins and power. this part has not been fitted as st andard because it has been reco gnis ed that the u s er will wish to select the connector type. through holes and surface mount pads allow for a number of connector options: ? sm pins fitted on top or under the pcb ? samtec tsm-125 -0x-x-dv ? sm sockets on t op or under the pcb ? samtec ssm-125-x-dv ? any through hole 50-way connector at 0.1? pitch. i / o conn mcu pi n symbol i / o conn mcu pi n symbol 1 n / a n o connect 2 n/ a 5 v 3 1 3 1 a v s s 4 n / a g n d 5 8 4 p 6 5 6 8 3 p 6 4 7 8 2 p 6 3 8 8 1 p 6 2 9 1 1 0 p 5 3 1 0 1 1 3 p g 4 1 1 1 1 4 p g 5 1 2 1 1 5 p g 6 1 3 1 2 1 v r e f 1 4 1 2 2 a v c c 1 5 1 1 7 p 4 0 1 6 1 1 8 p 4 1 1 7 1 1 9 p 4 2 1 8 1 2 0 p 4 3 1 9 1 2 3 p 4 4 2 0 1 2 4 p 4 5 2 1 1 2 5 p 4 6 2 2 1 2 6 p 4 7 2 3 1 2 7 p 5 4 2 4 9 3 s t b y n 2 5 1 2 9 p 5 6 2 6 1 2 8 p 5 5 2 7 6 1 p 6 1 2 8 1 3 0 p 5 7 2 9 5 9 p 2 7 3 0 6 0 p 6 0 3 1 5 7 p 2 5 3 2 5 8 p 2 6 3 3 5 5 p 2 3 3 4 5 6 p 2 4 3 5 5 3 p 2 1 3 6 5 4 p 2 2 3 7 5 1 p 1 7 3 8 5 2 p 2 0 3 9 4 9 p 1 5 4 0 5 0 p 1 6 4 1 4 6 p 1 3 4 2 4 8 p 1 4 14
i / o conn mcu pi n symbol i / o conn mcu pi n symbol 4 3 4 4 p 1 1 4 4 4 5 p 1 2 4 5 4 0 p 7 3 4 6 4 3 p 1 0 4 7 3 6 p 7 2 4 8 n/ a g n d 4 9 n / a n o connect 5 0 n/ a 3 v 3 t able 3-4: a uxiliar y i/o c onn e ctions 15
4. b oard o ptions 4.1. j u m per l inks the edosk has a two-ro w 8 pin header for selecting operation modes. 8 7 6 5 4 3 2 1 boot mo n e n mf w e n bf w e n f igure 4-1: j umper c onfiguration as default, jump ers for boot an d mf wen are fi ted. boot: boot/normal mode. fitted to link pin s 8-7 ? boot mode: mcu initialis es in 8-bit mode and boots from the 512kb boot flash. not fitted ? normal mode: mico n initialise s in 16 -bit mode and boots from the 4mb main flash. mon en: m oni tor enable. fitted to link pin s 6-5 ? enables the hitachi monit o r (when included in user code). not fitted ? program code runs with no monitor. mf wen: main flas h write e n able. fitted to link pin s 4-3 ? allows th e main flash to be written to by the mcu. not fitted ? main flash is write protected. bf wen: boot flas h write e n able. fitted to link pin s 2-1 ? allows th e boot flash to be written to by the mcu. not fitted ? boot flash is write protected. 4.2. rtc b ackup s up ply without a backu p supply to the rtc, time and d a te in formation is lost when the board is powere d down. two options are available on the edosk: 1. a cell battery ma y be fitted. 2. an auxiliary sup p ly of 1.3v to 3. 6v may be pr ovided to j8 ? a 2-pin through hole header (not fitte d). each of these o p tions may or may not be rechargeable. if however neither option is used or the backup supply fall s below 1.3v then the edosk board will cease to functio n when powered up unless a supply from vcc is provided. by default desig n this supply from vcc is provide d . the following diagram shows the circuit used for the rtc backup supply: 16
3v3 c e ll batter y j8 rt c b a ck u p d1 d2 r d1 provides the vcc supp ly and prevents the cell battery (o r auxiliary supply) from powering all of the board when p o wered down. d2 provides protection for the cel l battery (or auxiliary supply) agai nst accidenta l ch arging. r (when fitted) a llows charge current to be select ed or charging by the rtc device. the following options are availab l e: backup po wer op tio n com p o n en t co nfi gurati on com m en ts no cell battery, no auxiliary sup p ly, none rechargea ble cell battery, none rechargeable auxiliary supply d1 and d2 fitted. r not fitted. default configuration. no method of re charging cell or auxiliary supply. d1 and d2 fitted. r not fitted. default configuration. no method of re charging cell or auxiliary supply. d1 fitted. d2 optional. r=3.3/i char ge backup supp ly is charged through d1. rtc t r ickle char ge is not used. rechargeable cell battery, rechargeable auxiliary supply d1 not fitted. d2 optional. r=0 ohms. backup supp ly is charged through rtc t r ickle char ge network. edosk will not operate if backu p supply fails. 4.3. r emot e s wit c h both reset and nmi switches may be activated r e motely. by attaching 2-pin headers to j10 and j9, normally- open switches can be attached via flying lead s. j10 ? nmi j9 ? reset the nmi switch signal is de-bounced on the edosk board with a time constant t rc =0.47 seconds. the reset switch signal is de- bounced on the edosk board with time con s ta nts t rc( off) =0.03 seconds and t rc ( o n) =0.22 seconds. 4.4. c ry stal c hoice the mcu c r ystal frequency has b een chosen to support the fast est operation. the value of the crystal is 33.0000m hz. 17
the user may re place the hc49/u surface mounted at cut cryst a l with another of similar type with in the operating frequency of the mcu device. please refer to the hardware manual for the mcu for the valid operating rang e. another crystal is provided at 16 x 115200 (1.84 32mhz). this cr ystal output is f ed directly into the sck2 pin of the mcu allowing, with co rrect register set t ings, a fi xed serial baud rate of 115200bps with zero errors. the user may wish to ignore the serial clock oscillator i nput and use the system clock for baud rate generation ? register settings will nee d to be amended as per the follo wing example. example: the following ta ble shows the b aud rates and baud rate regist er (brr) setting required for each communicat i o n rate usin g the operating speed of 33.0000mhz (default). note that there are no zero erro r p e rcentages. baud rate regi ster set t ing s for serial co mm un icatio n ra tes us ing 33.0 000mhz s y s t e m cloc k smr setting: 0 1 2 3 com m . baud brr setti ng err ( % ) brr setti ng err ( % ) brr setti ng err ( % ) brr setti ng err ( % ) 110 inv a l i d i n v a l i d inv a l i d inv a l i d i n v a l i d inv a l i d 1 4 5 0 . 3 3 300 inv a l i d i n v a l i d inv a l i d i n v a l i d 2 1 4 0 . 0 7 5 3 0 . 5 4 1200 inv a l i d i n v a l i d 2 1 4 0 . 0 7 5 3 0 . 5 4 1 2 3 . 2 9 2400 inv a l i d i n v a l i d 1 0 6 0 . 3 9 2 6 0 . 5 4 6 4 . 0 9 4800 2 1 4 0 . 0 7 5 3 0 . 5 4 1 2 3 . 2 9 2 11. 9 0 9600 1 0 6 0 . 3 9 2 6 0 . 5 4 6 4 . 0 9 1 16. 0 8 19200 5 3 0 . 5 4 1 2 3. 2 9 2 1 1 . 9 0 0 1 6 . 0 8 38400 2 6 0 . 5 4 6 4 . 0 9 1 16. 0 8 i n v a l i d i n v a l i d 57600 1 7 0 . 5 4 3 1 1 . 9 0 0 1 1 . 9 0 i n v a l i d i n v a l i d 115200 8 0 . 5 4 1 1 1 . 9 0 0 4 4 . 0 5 i n v a l i d i n v a l i d t able 4-1 c rystal f requencies for r s 232 communication 4.5. r e m ov able c o mp one n t information . analogue and reference voltages to the mcu are, as default, is olated from the auxiliary i/o connector by not fitted 0805 resistors. to ma ke this connection the following resistors must be removed and re-soldered or replaced in the alternative positions deta ile d below: h8/ 2674r pi n remove fi t resi stor val u e avcc (pin 122) r25 r9 0 ?, 0 805 avss (pin 131) r7 r8 0 ?, 0 805 vref (pin 121) r11 r10 0 ?, 0 805 care must be t a ken not to da mage the t r acking around thes e components. only use soldering equipment designed for surface mount assembly and re work. 4.6. a dditional comp one n t information . the addition of a 0 ? resistor f i tte d in po sition r37 will permanently deacti vate the main flash. this is to be used w hen cs0n and/or cs1n are to be used by a n expansion bo ard. 18
5. s t art - up i nstr uc tion s 1. connect the edosk to a pc or notebook computer equipped with a nine pin d connector using a direct 1-1 cable (supplied). ho st pc ed osk 3 2 5 3 2 5 f igure 5-1: s erial c onnection to pc/n otebook with db-9 c onnector (s u ppl i e d ) 2. open a hyper te rminal set to a baud rate of 115200, 8 bits, no parity and 1 stop bit . 3. connect a power supply of +5v capable of prov iding at least 500m a (supplied: center +ve). 4. check boot flash write enable setting : no jumper fitted to j5 pin s 1-2 5. check main flash write enable setting: jumper is fitted to j5 pins 3-4 6. check monitor enable setting: n o jumper fitted to j5 pins 5-6 7. check boot mode setting: jumpe r is fitted to j5 pins 7-8 8. switch power on. 19
6. c ode d eve lopment incorporated into the mot file th at is programmed into the boot flash device is t he option to run the embedded test suite software (ets ). this software is availab l e to the user, via a hyper -terminal link an d contains a nu mber of functions including the choice of testing the major f unctions of the edosk and the option of downl oading user software to both the amd an d intel flash devices. 6.1. f lash p rogramming edosk hardware allows both bo ot and main flash memory to be programmed in system when th e appropriate write enab l e jumpers are fitted. when the edos k is first powered up in boot mode and a serial connection has b een made to a hyper terminal the user will be given the option to re-prog r am flash device s . the user may specify any valid s-record file to be programmed. 6.2. t es t m en u the tests in corporated in the bo ot flash allow for a majority of th e edosk to be verified ? for production and for prototype debugging. three main menu options are given to pr ogram flash, testing an d diagnosis. these lead to further menu options as shown below: pr o g ra m fl a s h te s t i n g dia g n o s i s bo o t f l a s h ma i n f l as h q ui c k en v i r o nm e n t a l bo o t f l a s h ma i n f l as h p r od uctio n sd r a m rt c ti m e r l e d & nm i et h e rn e t me m o r y eph l o o p - b a c k l o cal l o o p - b ac k c o nn e c t or l o o p - b a c k con f i g u r e m a c 6.3. hdi-m onitor the h8/2674 r has no dedicated debug port an d at present sw has not been developed to e nable a hdi mo nitor for the EDOSK2674. however, a mon_en (monitor enable) jumper has been provided for th is future feature. this jumper drives mcu port pin 30 low when fitted and high when not fitted. hdi -monitor code m a y be integrated with the user code and read th e monitor enable jumper setting to enable or disable the fe ature. 20
7. s oftw are the following m ap and register settings are for t he h8/2674r fi tted to the EDOSK2674 as stand ard i.e. with a system clo c k frequency of 33mhz. registers are subject to change dependi ng on the software requirements. 7.1. EDOSK2674 m emor y m ap the addressable memory add re ss space is split into ei ght areas, each capable of addressing 2mbytes. each area has a dedicated chip select signa l (cs0n ? cs7n). ? note that the s e signals are only enabled when pfcr0 registe r bits are set. mode of the syst em determines which memory resides in areas 0 and 1. the following table shows the EDOSK2674 me mory map and bus width. f r o m t o exter n al ar e a descr i p ti o n si z e b u s wi dt h mode : boot h ? 0 0 0 0 0 0 h ? 1 f f f f f c s 0 boot flash ( not e 1 ) 512kb x4 8 h?200000 h?3fffff cs1 (port pin low) main flash (page 0) 2mb 16 h?200000 h?3fffff cs1 (port pin high) main flash (page 1) 2mb mode : normal h?000000 h?1fffff cs0 main flash (page 0) 2mb 16 h?200000 h?3fffff cs1 main flash (page 1) 2mb mode : normal & boot h ? 4 0 0 0 0 0 h ? b f f f f f cs2, cs3, cs4, c s 5 s d r a m 8 m b 1 6 h ? c 0 0 0 0 0 h ? d f f f f f c s 6 e x p a n s i o n bo a r d 2 m b 8/ 1 6 h ? e 0 0 0 0 0 h ? e f f f f f c s 7 boot flash ( not e 1 ) 512kb x2 8 h ? f 0 0 0 0 0 h ? f 7 f f f f c s 7 t b d 0. 5 m b h ? f 8 0 0 0 0 h ? f b f f f f c s 7 lan chip ( not e 2 ) 2 5 6 k b h ? f c 0 0 0 0 h ? f f 3 f f f c s 7 t b d 2 0 8 k b h ? f f 4 0 0 0 h ? f f b f f f c s 7 on chip ram ( not e 3 ) 3 2 k b h ? f f c 0 0 0 h ? f f f b f f c s 7 ext e r nal address sp ace 15 kb h ? f f f c 0 0 h ? f f f e f f c s 7 i n t e rnal i / o regist ers 768b h ? f f f f 0 0 h ? f f f f 1 f c s 7 ext e r nal address sp ace 32b h ? f f f f 2 0 h ? f f f f f f c s 7 i n t e rnal i / o regist ers 224b t able 7-1: m emo r y m ap note 1: the same 512k of boot flash is mapped 4 ti mes over the 2 m b area of cs0 (in boot mode only) and 2 time s over the 1mb area. note 2: lan only occup i es 16 bytes (0x0 to 0xf), but is repeated throughout the 256kb mapped area. note 3: only if internal ram is enabled. 21
a r ea 0 (c s 0 n ) a r ea 1 (c s 1 n ) 0 0 000 0h 1 f fff fh 2 0 000 0h 3 f fff fh a r ea 6 (c s 6 n ) c 0 000 0h d f fff fh a r ea 7 (c s 7 n ) e 0 000 0h f f fff fh po r t p i n hi g h po r t p i n low a r ea 2 (c s 2 n ) 4 0 000 0h 5 f fff fh a r ea 3 (c s 3 n ) 6 0 000 0h 7 f fff fh a r ea 4 (c s 4 n ) 8 0 000 0h 9 f fff fh a r ea 5 (c s 5 n ) a 0 000 0h b f fff fh s dra m s dra m e x pans i on ma i n f l a s h ( pag e 0) ma i n f l a s h ( pag e 1) bo o t f l a s h m a in f l a s h ( pag e 0) ma i n f l a s h ( pag e 1 ) no rm a l mo d e boot m ode bo o t f l a s h bo o t f l a s h bo o t f l a s h bo o t f l a s h no rm a l & bo o t m ode bo o t f l a s h l a n , r a m , in t. i/o re g i s t e r s f igure 7-1: m emory m ap in normal mode the main flash pages 0 and 1 a r e mapped to areas 0 and 1 respectively. port pin 33 is not u s ed . the boot flash may only be accessed in area 7. in boot mode the main flash is mapped to area 1 only and drivin g port 33 low or high selects pa ge 0 or 1. the b oot flash is duplicated in a r eas 0 and 7. 22
7.2. h8/2674r r egis te r c onfiguration 7.2.1. b us c ontroller (bsc) bus width control re gister : abwc r (h? f f f e c0) = h?81 (b oo t) or h?80 ( n or mal ) bit no 7 6 5 4 3 2 1 0 bit name abw7 a b w 6 a b w 5 a b w 4 a b w 3 abw2 abw1 abw0 initial va lue 1 or 0 1 / 0 1 / 0 1 / 0 1 / 0 0 0 1 note: in boot mode (mcu mo de 2), abwcr is init ialized to 1. in normal mode (mcu mo de 1), abwcr is initial i zed to 0. in boot mode area 7 and 0 are mapped as 8-bit areas. in normal mo de only area 7 is mapped as 8-bit area. the sdram (abw2) is always mapped as 16-bit area. access state control re gister s: astcr (h? f ffec1) = h? ff b i t n o 7 6 5 4 3 2 1 0 bit n a m e a s t 7 a s t 6 a s t 5 a s t 4 a s t 3 a s t 2 a s t 1 a s t 0 i n i t i a l va l u e 1 1 1 1 1 1 1 1 all areas are designated as 3-st ate access space. wait contr o l registers: wtcr ah (h?fffec2) = h?27 bit no 15 14 13 12 1 1 1 0 9 8 bit name reserved w72 w71 w70 r e s e r v e d w 6 2 w 6 1 w 6 0 initial va lue 0 0 1 0 0 1 1 1 area 7 has 2 program wait states inserted. area 6 has 7 program wait states inserted. wtcr al (h? f ffec3) = h?77 b i t n o 7 6 5 4 3 2 1 0 b i t n a m e r e s e r v e d w 5 2 w 5 1 w 5 0 r e s e r v e d w 4 2 w 4 1 w 4 0 i n i t i a l va l u e 0 1 1 1 0 1 1 1 area 5 has 7 program wait states inserted. area 4 has 7 program wait states inserted. 23
wtcr bh (h?fffec4) = h?71 b i t n o 1 5 1 4 1 3 1 2 1 1 10 9 8 b i t n a m e r e s e r v e d w 3 2 w 3 1 w 3 0 r e s e r v e d w22 w21 w20 i n i t i a l va l u e 0 1 1 1 0 0 0 1 area 3 has 7 program wait states inserted. sdram has a cas latency of 2. wtcr bl (h? f ffec5) = h?23 (b oot) or h?22 (nor mal) bit no 7 6 5 4 3 2 1 0 bit name reserved w12 w11 w10 reserved w12 w11 w10 initial va lue 0 0 1 0 0 0 1 1 or 0 area 1 has 2 program wait states inserted. in boot mode, area 0 has 3 pro g ram wait states inserted. in normal mo de area 0 has 2 program wait states inserted. read str obe ti min g co ntr o l r e gister: rdnc r (h?fffec6) = h?00 b i t n o 7 6 5 4 3 2 1 0 b i t n a m e r d n 7 r d n r d n r d n r d n r d n r d n r d n i n i t i a l va l u e 0 0 0 0 0 0 0 0 in all areas the / rd signal is neg ated at the end of the read cycle . cs assertion period control registers: csacr h (h?fffec8) = h?80 bit no 7 6 5 4 3 2 1 0 bit name csxh7 c s x h 6 c s x h 5 c s x h 4 csxh 3 c s x h 2 c s x h 1 c s x h 0 initial va lue 1 0 0 0 0 0 0 0 in area 7 basic b u s interface access, the /csn an d address assertion period (t h ) is extended. csacr l (h?fffec9) = h?80 bit no 7 6 5 4 3 2 1 0 bit name csxt7 c s x t 6 c s x t 5 c s x t 4 csxt 3 c s x t 2 c s x t 1 c s x t 0 initial va lue 1 0 0 0 0 0 0 0 in area 7 basic b u s interface access, the /csn an d address assertion period (t t ) is extended. 24
burst rom i n te rface contr o l register: bromcr h (h?fffec a ) = h?d3 (b oo t) or h?a3 (n orma l) bit no 7 6 5 4 3 2 1 0 bit name bsrmn bstsn2 bstsn1 bstsn0 r e s e r v e d r e s e r v e d bswdn1 bswdn0 initial va lue 1 1 or 0 0 or 1 1 or 0 0 0 0 0 area 0 burst rom enabled with maximum of 4 words. in boot mode 6-cycle burst sta t es are used. in no rmal mode 3- cycle bur st states ar e used. bromcr l (h?fffec b ) = h?a3 bit no 7 6 5 4 3 2 1 0 bit name bsrmn bstsn2 bstsn1 bstsn0 r e s e r v e d r e s e r v e d bswdn1 bswdn0 initial va lue 1 0 1 0 0 0 0 0 area 1 burst rom enabled with maximum of 4 words. 3- cycle bur st sta t es ar e used. bus control re gister: bcr (h?fffecc) = h?0100 b i t n o 1 5 1 4 1 3 1 2 1 1 1 0 9 8 bit n a m e b r l e b r e q o e r e s e r v e d i d l c i c i s 1 i c i s 0 w d b e waite i n i t i a l va l u e 0 0 0 0 0 0 0 1 b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d i c i s 2 r e s e r v e d r e s e r v e d i n i t i a l va l u e 0 0 0 0 0 0 0 0 external bus release and bus request disabled, no idle cycle s in serted, wait pin enabled dram c o ntrol r e gister: dram cr (h?fffed0) = h?84b4 bit no 15 14 1 3 1 2 1 1 10 9 8 bit name oee rast r e s e r v e d c a s t r e s e r v e d rmts2 rmts1 rmts0 initial va lue 1 0 0 0 0 1 0 0 bit no 7 6 5 4 3 2 1 0 bit name be rcdm dds edds reserved mxc2 mxc1 mxc0 initial va lue 1 0 1 1 0 1 0 0 oe/cke signal output enabled, ras is asserted from ? falling edge in t 1 cycle, 2-state colu mn address cycle, continuous synchronous dram space access in fast p age mode, 8-bit shift, row address bit s a23 to a12 used for com parison, the precharge-sel is a1 5 to a12 of the colu mn address. 25
sdram n o tes: prior to using the sdram the m ode must be set in the smr (sdram mode regi ster). the smr should be set to the value b?0000 001 0 0000 ? cas late ncy 2, burst 1. this is a c hieved b y a write cycle to the sdram at a n address equal to the required smr value when in configuration mode. the address to set the smr sh ould be h?4000 40 ? sdram starts at area h?400000 and the smr value must be shifted to compe n sate for word a ccess. example: 1. configure all other sdram regi sters. 2. dramcr = 0x85b4; //smr configuration mode 3. sdram_control = 0; // whe r e sdram_control is h?400040 4. dramcr = 0x84b4; //return to sdram o perating mode dram access control regis t e r : draccr (h? f ffed2) = h?0000 b i t n o 1 5 1 4 1 3 1 2 1 1 1 0 9 8 bit n a m e d r m i r e s e r v e d t p c 1 t p c 0 s d w c d r e s e r v e d r c d 1 r c d 0 i n i t i a l va l u e 0 0 0 0 0 0 0 0 b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d c k s p e r e s e r v e d r d x c 1 r d x c 0 i n i t i a l va l u e 0 0 0 0 0 0 0 0 idle cycle not in serted, 1-state pre-charge, cas latency enabled, no wait between ras and cas cycles. no clock su spen d, 1-state read d a ta extension cycle. refresh control register : refcr (h? f ffed4) = h?0188 b i t n o 1 5 1 4 1 3 1 2 1 1 10 9 8 bit name cmf cmie rcw1 rcw0 reserved rtck2 rtck1 rtck0 i n i t i a l va l u e 0 0 0 0 0 0 0 1 b i t n o 7 6 5 4 3 2 1 0 bit name rfshe cbrm rlw1 rlw0 slfrf t p c s 2 t p c s 1 t p c s 0 i n i t i a l va l u e 1 0 0 0 1 0 0 0 no wait states between cas and ras, ref count on ? /2 enable refresh control, no waits for cas-b e fo re-ras refres h c y cl e, self ref r esh e nab le d, zero states i n the prech a rge c y cl e immedi atel y after self refreshin g . 26
refresh timer counter : rtc n t (h? f ffed6 ) = h? ff b i t n o 7 6 5 4 3 2 1 0 bit n a m e rtc n t 7 r t c n t 6 r t c n t 5 r t c n t 4 rtc n t 3 r t c n t 2 r t c n t 1 r t c n t 0 i n i t i a l va l u e 1 1 1 1 1 1 1 1 refresh time c ons tan t regis t er: rtc o r (h? f ffed7) = h? ff bit no 7 6 5 4 3 2 1 0 bit name rtc o r7 rtc o r6 rtc o r5 rtc o r4 rtc o r3 rtc o r2 rtc o r1 rtc o r0 initial va lue 1 1 1 1 1 1 1 1 compare refres h count with 0xff 7.2.2. i nte rrup t c o n troller the edosk267 4 only uses the f o llowing interrupts: ? irq5n ? main fl ash ? irq0n ? lan controller ? irq1n - irq5n ? expansion conn ector ? nmi ? switch interru pt co ntr o l regis t er: intcr (h? f fff31) = h?08 b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d i n t m 1 i n t m 0 nmieg r e s e r v e d r e s e r v e d r e s e r v e d i n i t i a l va l u e 0 0 0 0 1 0 0 0 nmi is rising edg e triggered. interrupt control mod e 0 irq pin select register : itsr ( h ?f ffe1 6 ) = h? ff3 f bit no 15 14 13 12 11 10 9 8 bit name its15 its14 its13 its12 its11 its10 its9 its8 initial va lue 1 1 1 1 1 1 1 1 bit no 7 6 5 4 3 2 1 0 bit name its7 its6 its5 its4 its3 its2 its1 its0 initial va lue 0 0 1 1 1 1 1 1 irq15 - ir q8 ? port 2 irq7,6 ? port 5 7 , 56 irq5 -ir q 0 ? port 8 27
7.2.3. s er ia l c ommunication i nte r face 2 serial extensio n mo de re giste r : semr (h? f ffda8) = h?00 b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d a b c s a c s 2 a c s 1 a c s 0 i n i t i a l va l u e 0 0 0 0 0 0 0 0 basic clo ck is external; this register is not used. serial mode re gister_2: smr_2 (h? f fff88) = h?00 bit no 7 6 5 4 3 2 1 0 bit name c/a chr pe o/e stop mp cks1 cks0 initial va lue 0 0 0 0 0 0 0 0 asynchronous, 8 - bit, no parity, 1-stop bit, clock source ? bit ra te re gister_2: brr_2 (h?ffff89) = h? ff b i t n o 7 6 5 4 3 2 1 0 bit n a m e b r r 7 b r r 6 b r r 5 b r r 4 b r r 3 b r r 2 b r r 1 b r r 0 i n i t i a l va l u e 1 1 1 1 1 1 1 1 this register is n o t used. serial control register_2 : scr_2 (h? f fff8a) = h?32 bit no 7 6 5 4 3 2 1 0 bit name tie rie te re m p i e t e i e cke1 cke0 initial va lue 0 0 1 1 0 0 1 0 interrupt settings depend on sw, external clock input 16 times bit rate. smart card mode regis t er_2: scmr_2 ( h ?f f ff8e) = h?f2 b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d s d i r s i n v r e s e r v e d s m i f i n i t i a l va l u e 1 1 1 1 0 0 1 0 smart cart inte rf ace mode not used. 28
7.2.4. w atchdog t im er timer c o n t rol/ status regis t er : tcsr (h?ffffbc) = h?18 b i t n o 7 6 5 4 3 2 1 0 bit n a m e o v f w t / i t t m e r e s e r v e d r e s e r v e d c k s 2 c k s 1 c k s 0 i n i t i a l va l u e 0 0 0 1 1 0 0 0 timer c o u n ter : tcn t (h?ffffb c-write / h? ffffbd -read) = h? 00 tcnt is an 8-bit readable/writable up-counter . tcnt is initialized to h'00 when the tme bit in tcsr is cleared to 0. reset control/ status regis t er : rstcsr (h? f f ffbe ) = h?1 f b i t n o 7 6 5 4 3 2 1 0 bit name wovf rste reserved reserv e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d i n i t i a l va l u e 0 0 0 1 1 1 1 1 to prevent accidental overwriting, access of wdt registers is diffe rent from othe r registers. the wdt may be used to drive t he ?timer? led when the count er overflows. this, however , is a very short perio d and in order to see the led with the naked eye th e wdt must be forced to overflow repeatedly. example to keep led on: tcsr = 0xa500 ; // clear lower byte. tcsr = 0xa578 ; // setup & enab le the watchdog timer. while( 1) { if( rstcsr & 0 x 0080 ) // detect overflow and reset wdt. { rstcsr = 0xa500; // clear watchdog overflow bit. tcsr = 0xa57 8 ; // clear ove r flow bit and enable wdt. } } 7.2.5. io p ort po rt fu n c t i on co nt ro l reg i st er 0: pfcr0 (h?fffe32) = h?ff b i t n o 7 6 5 4 3 2 1 0 bit n a m e c s 7 e c s 6 e c s 5 e c s 4 e c s 3 e c s 2 e c s 1 e c s 0 e i n i t i a l va l u e 1 1 1 1 1 1 1 1 enable all cs signals 29
po rt fu n c t i on co nt ro l reg i st er 1: pfcr1 (h?fffe33) = h?ff b i t n o 7 6 5 4 3 2 1 0 bit n a m e a 2 3 e a 2 2 e a 2 1 e a 2 0 e a 1 9 e a 1 8 e a 1 7 e a 1 6 e i n i t i a l va l u e 1 1 1 1 1 1 1 1 enable all addre ss line s (a21 and a23 used for sdram bank select) po rt fu n c t i on co nt ro l reg i st er 2: pfcr2 (h?fffe34) = h?0d b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d asoe lwroe oes dmacs i n i t i a l va l u e 0 0 0 0 1 1 0 1 pf6 is designate d as /as output pin. pf3 is designate d as /lwr output pin. p35 is designate d as sdram cke output pin. pf75 to pf70 are designated as dmac control pins mcu por t 3 signal na me fu ncti on 30 mon_enn monitor enable. active low. ena b les monitor functions embedde d in software. 31 i2c_scl i2c bus serial clock for rtc 32 i2c_sda i2c bus serial d a ta signal to/fro m rtc 33 mflash_page main flash page select. used in boot mode only. low selects p age 0, high selects page 1 34 sdram_csn sdram chip select. active low. enables the sd ram device. 35 sdram_cke sdram clock e nable. active lo w. enables the sdram clock in put. port 3 da ta dir ection regis t er : p3ddr (h?fffe22) = h?3a bit no 7 6 5 4 3 2 1 0 bit name reserved reserved p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr initial va lue 0 0 1 1 1 0 1 0 the individual bits of p3ddr specify input or outpu t for the pins of port 3 ? ?0? input, ?1? output. port 3 da ta register: p3dr (h? f fff62) = h?00 b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d p 3 5 d r p34dr p 3 3 d r p 3 2 d r p 3 1 d r p 3 0 d r i n i t i a l va l u e 0 0 0 0 0 0 0 0 p3dr stores output data for the port 3 pins. 30
enable sdram cs. port 3 re gister: port3 (h? f fff52) b i t n o 7 6 5 4 3 2 1 0 b i t n a m e r e s e r v e d r e s e r v e d p 3 5 p 3 4 p 3 3 p 3 2 p 3 1 p 3 0 i n i t i a l va l u e 0 0 x x x x x x read only, value determined by the states of pins p35 to p30. port 3 open dr ain contr o l re gister: p3odr (h? f f f e 3c) = h?06 b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d p 3 5 o d r p 3 4 o d r p 3 3 o d r p32odr p31odr p30odr i n i t i a l va l u e 0 0 0 0 0 1 1 0 i2c signals are nmos open -dra in port a da ta dir ection regis t er : paddr (h? f ffe29) = h?ff bit no 7 6 5 4 3 2 1 0 bit name paddr paddr paddr paddr paddr paddr paddr paddr initial va lue 1 1 1 1 1 1 1 1 the individual bits of paddr specify input or out put for the pins of port a ? ?0? input, ?1? output. port f data dir ection regis t er : pfddr (h? f ffe2e) = h?fe bit no 7 6 5 4 3 2 1 0 bit name pfddr pfddr pfddr pfddr pfddr pfddr pfddr pfddr initial va lue 1 1 1 1 1 1 1 0 the individual bits of pfddr sp ecify input or out put for the pins of port f ? ?0? input, ?1? output. set all as output s except pf0 (waitn) port g data direction regis t er : pgdd r (h? f ffe2f) = h?0 f b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d pgdd r p g d d r p g d d r pgdd r pgdd r pgdd r pgdd r i n i t i a l va l u e 0 0 0 0 1 1 1 1 the individual bits of pgddr sp ecify input or out put for the pins of port g ? ?0? input, ?1? output. 31
port h da ta dir ection regis t er : phddr (h? f fff74) = h?0f b i t n o 7 6 5 4 3 2 1 0 bit n a m e r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d phddr phddr phddr phddr i n i t i a l va l u e 0 0 0 0 1 1 1 1 the individual bits of phddr sp ecify input or out put for the pins of port h ? ?0? input, ?1? output. 32
8. m ec ha nica l d ra wing the mechanical drawing has been included here f o r the user to de velop add-on boards and face plates. 33
9. d esigning an e xp ansion c ar d 9.1. m e chanic a l the expansion card should be designed using the following di mensions (viewed from the top looking through the board at the connector): the jae connector kx15-140k2d (shown ) is fitted to the under-side of the expansion card to mate with kx14- 140k5d of the main board (in t h is case the ed osk2674) with board to board space of 7mm. components fitted to the under-side of the expansion card must have a maximum heig h t of 2mm. both connectors are surface m ounted and therefore another kx14-140k5d may be f i tted to t he top-side of t he expansion card to allow stacking . the 4 off 2.7mm holes in the cor ners are for stan d-off fixings. 9.2. f unctional consideration must be given to t he following con necting signa ls. reset signal the expansion connector has a dedicated active low reset signal (resn). when low all de vices f i tted to th e plug-in board should be reset. EDOSK2674 limitations- resn signal ma y be used. system cl ock the expansion connector has a dedicated system clock signa l (ckio). 34
this clock may b e used for bus cycle tim i ng but may vary in frequency dependin g upon the main board used. it is recommended that this clo c k is correctly terminated and/or buffered if being used. EDOSK2674 limitations- ckio signal may be used but is not buffered. chip selec t there are 7 acti ve low chip se le ct signals dedi ca ted to the expan sion connector (cs0n to cs6n). theses are used to select 7 area s of external memory. to avoid content ion the plug-in h a rdware should have the facility t o select which of these is to be u s ed. EDOSK2674 limitations- boot mode (h8 mode 2: 8-bit): cs0n may be used if the amd boot flash is removed. cs1n may be used if r37 0 ? resistor is fitted. normal mode (h8 mode 1: 16-bit): cs0n and cs1n may be used if r37 0 ? resistor is fitted. note that in this mode areas 0 and 1 can not be isolated. cs2n to cs5n are not connected. cs6n may be used. address bus there are 26 ad dress lines ded icated to the expa nsion connector (a0 to a25). this allows for address mapping of 2^26 bytes = 64mb. EDOSK2674 limitations- a0 to a23 may b e used (16mb maximum). a24 and a25 are not connected data b u s there are 32 da ta lines dedicate d to the expansion connector (d0 to d31). this allows data to be accessed as byte (8 -bit), word (16 - bit) or long (32-bit). EDOSK2674 limitations- d0 to d15 may be used (byte or word access). d16 to d31 are not connected. note: for an 8 - b i t mapped area d8 to d15 must be used. read-wri te str obe the expansion connector has a dedicated read-write signal (rwn). high indicates a read cycle and l o w indicates a w r ite cycle. EDOSK2674 limitations- rwn signal is n o t connected. 35
read str obe the expansion connector has a dedicated active low read strobe (rdn ). EDOSK2674 limitations- rdn signal may be used. write strobe there are 4 acti ve low write e nable signals dedicated to the exp ansion connecto r (we0n to we3 n ). a 32-bit data bu s may be separated into 4 bytes, the wr ite enable signals are used to determ i ne which of those bytes are to be written. EDOSK2674 limitations- we0n may be used to enable write data on d0 to d7. we1n may be used to enable write data on d8 to d15. we2n and we3n are not connected. note: for an 8 - b i t mapped area we1n must be used. bus str obe the expansion connector has a dedicated active low bus strobe (bsn). when low, this signifies the beg inning of a bus cycle or it may be used for latchin g the address while in mpx mod e . EDOSK2674 limitations- bsn signal ma y be used. note: h8s2674 r does not support mpx mode. wait there are 4 acti ve low wait sig nals dedicated t o the expansion connector (wait0n to wait3n). these are used to hold off the bus cycle until the device being a c cessed is ready. to avoid content ion the plug-in h a rdware should have the facility t o select which of these is to be u s ed. EDOSK2674 limitations- wait0n may be used. wait1n to wait3n is not conne cted. interrupts there are 8 inte rrupt request signals dedicated t o the expansion connector (irq1 n to irq8n). these are used to interrupt the main board proce ssor. depending upon the m cu irq may be level and/or ed ge triggered. to avoid content ion the plug-in h a rdware should have the facility t o select which of these is to be u s ed. EDOSK2674 limitations- irq1n to irq4n may be used. irq5n may be u s ed, but is also used by the main flash. irq6n to irq8n are not connected. direct memory access 36
there are 2 dm a request and 2 dma acknowle dge, all a c ti ve low, signals dedicated to the expansion conne ct o r (dre q0n, dre q1n, dack0n a nd dack1n). these are used by the plug-in ha rdware to reque st and acknowle dge a faster memory access. to avoid content ion the plug-in h a rdware should have the facility t o select which of these is to be u s ed. EDOSK2674 limitations- all dma signa ls may be used. 37
10. a dditiona l i nforma tion for details on ho w to use hitachi embedded workshop (hew) refe r to the hew ma nual availab l e on the cd o r f r om the web site. for information about the h8 series microcomput ers refer to the h8 series hard ware manual for information about the assem b ly language, ref e r to the h8 series programming manual furthe r information available for t h is product can be found on the hmse web site at: http://www.hmse .com/products/edosk general informat ion on hitachi microcom puters can be found at the following url. global: http://www.hitachisemiconductor.com/ 38

▲Up To Search▲

Price & Availability of EDOSK2674

	To Download EDOSK2674 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .